Electronic designs for large systems may include millions of gates and megabits of embedded memory. Of the tasks required in managing and optimizing electronic designs on a target device, synthesis, placement, and routing utilizing available resources can be among the most challenging and time consuming. The complexity of large systems often requires the use of computer aided design (CAD) or electronic design automation (EDA) tools to manage and optimize designs. CAD tools perform the time-consuming tasks of synthesis, placement, and routing on a target device.
Placement currently accounts for approximately 50% of design time in large systems. The density of today's target devices such as field programmable gate arrays (FPGAs) is outpacing increases in processor speed and the rate in which CAD procedures operate, leading to increases in placement compile times. One approach used to address this problem is to use hardware assisted placement in lieu of placement algorithms provided by CAD tools.
Hardware assisted placement techniques of the past suffered from a number of limitations associated with deriving the cost metrics used in placement. For example, hardware assisted placement techniques of the past suffered from using information that was stale when computing the bounding box cost of a net used to bound the terminals for the net. Hardware assisted placement techniques of the past also failed to provide consideration for timing critical paths which resulted in the maximum frequency at which a design can run to be adversely impacted.
Thus, what is needed is a method and apparatus for performing hardware assisted placement that efficiently and accurately derives cost metrics used in placement.